Satyaveer Singh Mahecha
- Industry experience in ASIC Verification, Validation, Emulation, Design and Development - Architecture, Design and Implementation of Verification Environment... | San Francisco, California, United States
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Satyaveer Singh Mahecha’s Emails sa****@ge****.com
Satyaveer Singh Mahecha’s Phone Numbers No phone number available.
Social Media
Satyaveer Singh Mahecha’s Location San Francisco, California, United States
Satyaveer Singh Mahecha’s Expertise - Industry experience in ASIC Verification, Validation, Emulation, Design and Development - Architecture, Design and Implementation of Verification Environment for Autonomous Vehicle sensor processors & network subsystem, analog/mixed-signal/DSP centric products for network communication applications, High Speed Optical Coherent Transceivers, Fixed Function blocks in GPU pipeline, USB, PCIe and AMBA (AXI, AHB, APB) protocols - SoC block level and top level verification experience using coverage driven, constrained-random generation methodology and Mixed Signal Verification - Development of verification components using SV-TB with UVM, OVM & VMM, OV/NTB with RVM, ‘e’, SCV, C and Verilog
Satyaveer Singh Mahecha’s Current Industry Cruise
Satyaveer
Singh Mahecha’s Prior Industry
Cruise
|
Aeonsemi
|
Inphi
|
Qualcomm
|
Cisco
|
Hp
|
Einfochips
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Work Experience
Cruise
Senior Soc Verification Engineer
— Present
Aeonsemi
Principal Engineer, Design Verification
Thu Jan 01 1970 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 1970 00:00:00 GMT+0000 (Coordinated Universal Time)
Inphi
Principal Engineer, Design Verification
Thu Jan 01 1970 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 1970 00:00:00 GMT+0000 (Coordinated Universal Time)
Qualcomm
Staff Engineer, Verification
Thu Jan 01 1970 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 1970 00:00:00 GMT+0000 (Coordinated Universal Time)
Cisco
Design Verification Engineer
Thu Jan 01 1970 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 1970 00:00:00 GMT+0000 (Coordinated Universal Time)
Hp
Hardware And Electrical Engineer
Thu Jan 01 1970 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 1970 00:00:00 GMT+0000 (Coordinated Universal Time)
Einfochips
Asic Verificaiton Engineer
Thu Jan 01 1970 00:00:00 GMT+0000 (Coordinated Universal Time) — Thu Jan 01 1970 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Satyaveer Singh Mahecha Email Addresses
FAQ About Satyaveer Singh Mahecha
-
Satyaveer Singh Mahecha is located at
San Francisco, California, United States -
Satyaveer Singh Mahecha is a
- Industry experience in ASIC Verification, Validation, Emulation, Design and Development - Architecture, Design and Implementation of Verification Environment for Autonomous Vehicle sensor processors & network subsystem, analog/mixed-signal/DSP centric products for network communication applications, High Speed Optical Coherent Transceivers, Fixed Function blocks in GPU pipeline, USB, PCIe and AMBA (AXI, AHB, APB) protocols - SoC block level and top level verification experience using coverage driven, constrained-random generation methodology and Mixed Signal Verification - Development of verification components using SV-TB with UVM, OVM & VMM, OV/NTB with RVM, ‘e’, SCV, C and Verilog Cruise -
Satyaveer Singh Mahecha currently works in the
Cruise -
Satyaveer Singh Mahecha specializes in
- Industry experience in ASIC Verification, Validation, Emulation, Design and Development - Architecture, Design and Implementation of Verification Environment for Autonomous Vehicle sensor processors & network subsystem, analog/mixed-signal/DSP centric products for network communication applications, High Speed Optical Coherent Transceivers, Fixed Function blocks in GPU pipeline, USB, PCIe and AMBA (AXI, AHB, APB) protocols - SoC block level and top level verification experience using coverage driven, constrained-random generation methodology and Mixed Signal Verification - Development of verification components using SV-TB with UVM, OVM & VMM, OV/NTB with RVM, ‘e’, SCV, C and Verilog -
Satyaveer Singh Mahecha speaks the following languages:
No languages available. -
Satyaveer Singh Mahecha has prior experience in the following industries:
Aeonsemi , Inphi , Qualcomm , Cisco , Hp , Einfochips -
Satyaveer Singh Mahecha has the following professional experience:
Cruise , Aeonsemi , Inphi , Qualcomm , Cisco , Hp , Einfochips . -
You can view Satyaveer Singh Mahecha’s
LinkedIn profile at LinkedIn URL. -
Satyaveer Singh Mahecha’s work email addresses are
[email protected] . -
Satyaveer Singh Mahecha works at
Cruise
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